Overview
Z4 se yon pwofesyonèl kontwolè ekspozisyon dirije. Kòm splicer videyo, processor and sender
in one combined, Z4 gen gwo kapasite nan resepsyon siyal videyo, processing and
transmission. It achieves excellent high-definition images and flexible image control
fonksyone. Z4 can be applied to popular rental display and common fixed display
perfectly.
Karakteristik
Video input ports including 1xHDMI(ak bouk), 1xdvi(ak bouk), SDI×2, VGA × 1;
Input resolution up to 1920×;
Support PIP and picture window roaming, the location and size of PIP can be adjusted freely;
Support 12bit HD video source;
Kapasite chaje: 2.3 milyon piksèl; Maksimòm Lajè: 4096 piksèl, Wotè maksimòm: 4096 piksèl;
Support splicing and cascading among several controllers with synchronization strictly;
Support brightness and chromaticity adjustment, transfòmasyon gam koulè;
Support zero latency of sending;
Support improved gray-scale at low brightness;
Support HDCP1.4;
Konpatib ak tout kat k ap resevwa yo , kat multifonksyon, optical fiber transceivers of Colorlight.
The Front Panel
| NON | Non | Fonksyon |
| 1 | 1.8-inch LCD | Display operation menu and system information |
| 2 | Knob | Turning knob to select or adjust |
| Ok/span>Enter key | ||
| 3 | Function keys | ESC/span>Escape current operation or selection |
| Bright/span>Brightness option | ||
| Glase：Freeze screen | ||
| Pip PIP switch | ||
| 4 | Selection keys | DVI/HDMI/SDI1/SDI2/VGA/span>set up video source input |
The Back Panel
| Entèfas Antre | ||
| 1 | Dmi | HDMI1.4 D 'ak bouk |
| 2 | DVI | Antre DVI ak bouk |
| 3 | Sdi | 2x3G-SDI inputs |
| 4 | VGA | Antre VGA |
| Entèfas Sòti | ||
| 1 Fiber Output | 2 singlemode LC fiber outputs | |
| 2 Gigabit Ethernet | 4 Sorti Gigabit Ethernet | |
| 3 Dmi | HDMI monitoring output | |
| Kontwole Entèfas | |
| 1.100M Ethernet | Kontwòl rezo (kominikasyon ak PC, oswa aksè rezo) |
| 2.USB_OUT | USB pwodiksyon, kaskad ak pwochen kontwolè |
| 3.USB_IN | Antre USB, connection with PC to configure parameters of display image |
| 5.GENLOCK_LOOP | Genlock signal loop output |
